Japanese Laid-Open Patent Application No. 11-3243 discloses a data processing unit capable of separately testing the microprocessor or the memory mounted in the multi-chip module. To that end, when output enable signals are active, and control signals are turned to a high level, the output enable signals input to the output enable terminal of the memory are inactivated and external output enable signals are activated. When secondary cache output enable signals are not active, the output enable signals are inactivated. Therefore, when the control signals are at the high level, since the memory does not perform output even in the read cycle of a secondary cache, the single body test of the microprocessor can be performed.